1. Field of the Invention
This invention relates to a digital/analog converting device, and more particularly to a digital/analog converting device that employs a plurality of digital/analog converters to carry out conversion with high accuracy.
2. Description of the Prior Art
The digital/analog converting devices are employed in various equipment such as information communication and audio instruments. In recent years, the digital/analog converting devices are required to handle large bits for the following reasons.
The digital/analog converting device incorporated in a digital audio instrument such as a CD (compact disc) player and a DAT (digital audio taperecorder) basically comprises a 16 bit digital/analog converter (hereinafter referred to as DAC) and a low pass filter (hereinafter referred to as LPF). An output of DAC includes folding components with a carrier that is an integer multiple of a sampling frequency. To remove the folding components of DAC, LPF shall have steep damping characteristics. However, if the damping characteristics of LPF be too steep, it would result in increase of a ripple and deterioration of phase characteristics of a passband.
To cope with this problem, a digital filter for over-sampling tends to be disposed before DAC. The digital filter equivalently increases a sampling frequency of a digital signal to be inputted to DAC to shift folding components of the digital signal toward a high-frequency side so that LPF may not be required to have an excessive degree of damping characteristics. Arranging the digital filter before DAC is known as very effective to reduce a load on LPF. However, it has a drawback that the number of bits of output data increases due to repetitive operation. If the number of bits converted by DAC is kept at 16, fractions of output data of the digital filter shall be discarded or rounded up or down with respect to a threshhold of five. Then, repeated quantization of errors of the rouding up/down cause many noises. Therefore, if the digital filter is disposed, it will be necessary to arrange a large-bit DAC to minimize such noises.
Generally, a weight resistance of DAC is trimmed to satisfy a nonlinear error of .+-.1/2LSB (least significant bit). Even with this, the number of bits in the order of 16 is nearly a limit at present. A Japanese patent publication No. 55-36215 proposes a digital/analog converting device that employs a plurality of small bit DACs to realize digital/analog conversion equivalent to that of a large-bit DAC. As shown in FIG. 9 of the accompanying drawings, this prior art digital/analog converting device employs a 5 bit DAC 1 for upper 5 bits and a 6-bit DAC 2 for lower 5 bits and for 1 bit for correcting an output error of DAC 1, to achieve digital/analog conversion with 10-bit accuracy. This digital/analog converting device comprises a ROM (read only memory) 3 storing digital data for correcting the output error of DAC 1 with the use of DAC 2; a logic operation circuit 4 for adding digital data read out of ROM 3 in response to a digital signal of the upper 5 bits to a digital signal of the lower 5 bits; and an analog adder 5 for adding an analog output from DAC 1 to an analog output from DAC 2 at a ratio of 1:1. DACs 1 and 2 are selected such that an output of DAC 1 for an LSB is identical to an output of DAC 2 for an MSB (most significant bit). With such arrangement, an analog output converted by DAC 1 from the digital signal of upper 5 bits may contain an output error in the range of .+-.1/2LSB, which, however, can be corrected by an analog output from DAC 2.
In the digital/analog converting device of the above-mentioned prior art, if an output (a theoretical value) of DAC 1 for an LSB is precisely identical to an output (a theoretical value) of DAC 2 for an MSB and if an adding ratio of the analog adder 5 is correctly 1:1 without an error, an output Va of the analog adder 5 for LSB of DAC 1 will at last be equal to an output Vb of the analog adder 5 for MSB of DAC 2. Then, an analog output from the adder 5 for the upper 5 bits of DAC 1 will be continuous to an analog output from the adder 5 for the lower 5 bits of DAC 2. Thus, required 10 bit digital/analog conversion is achieved.
ln practice, however, due to a limited accuracy of the adding ratio of the analog adder 5, the outputs Va and Vb will not always be equal to each other. To cope with this, an output gain of DAC 1 or 2 shall be adjusted, or the adding ratio of the analog adder 5 shall be adjusted such that the outputs Va and Vb correctly agree with each other. However, such adjustment requires a strict accuracy and therefore is very hard to achieve. In addition a variable resistor employed for the adjustment is generally vulnerable to temperature changes and aging to degrade the digital/analog conversion. It may be considered to connect a plurality of fixed resistors in parallel to adjust the adding ratio of the analog adder 5, which is laborious and not proper for mass production.